1. Technical Field
The invention relates to a memory cell in accordance with the preamble of patent claim 1 and to memory cell arrangements which are composed of such memory cells. The invention also relates to a method for fabricating a memory cell and a memory cell arrangement.
2. Background Information
In dynamic random access memory cell arrangements, it is virtually exclusively what are known as single-transistor memory cells which are used. A single-transistor memory cell comprises a read or select transistor and a storage capacitor. The information is stored in the storage capacitor in the form of an electric charge which represents a logic 0 or a logic 1. Actuating the read transistor via a word line allows this information to be read via a bit line. The storage capacitor must have a minimum capacitance for reliable storage of the charge and, at the same time, to make it possible to differentiate the information item which has been read. The lower limit for the capacitance of the storage capacitor is currently considered to be 25 fF.
Since the storage density increases from memory generation to memory generation, the surface area required by the single-transistor memory cell must be reduced from generation to generation. At the same time, the minimum capacitance of the storage capacitor has to be retained.
Up to the 1 Mbit generation, both the read transistor and the storage capacitor were produced as planar components. Beyond the 4 Mbit memory generation, the area taken up by the memory cell was reduced further by using a three-dimensional arrangement of read transistor and storage capacitor. One possibility is for the capacitor to be produced in a trench (cf. for 5 example K. Yamada et al., Proc. Intern. Electronic Devices and Materials IEDM 85, pp. 702 ff). In this case, a diffusion region which adjoins the wall of the trench and a doped polysilicon filling arranged in the trench act as electrodes for the storage capacitor. Therefore, the electrodes of the storage capacitor are arranged along the surface of the trench. In this way, the effective surface area of the storage capacitor, on which the capacitance is dependent, is increased with respect to the space taken up by the storage capacitor on the surface of the substrate, which corresponds to the cross section of the trench.
In the memory cells which have been in series production since the 4 Mbit memory generation, the upper capacitor electrode of the trench capacitor is electrically connected to a horizontal select transistor, which is arranged above the trench capacitor and laterally offset with respect thereto, via a conductive bridge of polycrystalline silicon. However, an arrangement of this type, on account of the horizontally oriented select transistor, requires a relatively large amount of space, so that a further increase in the packing density of the memory cells is only possible to a limited extent.
For some time, therefore, a different variant of a memory cell with trench capacitor has been proposed, in which the select transistor is arranged as a vertical MOSFET transistor directly above the trench capacitor.
EP 1 077 487 A2 describes a DRAM memory cell with trench capacitor in which a capacitor is formed in a lower section of a trench formed in a semiconductor substrate and a select transistor is formed in an upper section of the trench. In this case, the channel region of the select transistor extends along the side wall of the trench, between a first source/drain connection, which is coupled to the upper capacitor electrode of the trench capacitor, and a second source/drain connection, which is arranged close to the substrate surface. The gate electrode is situated in the trench above the capacitor, and there is a gate oxide layer at the interface with the channel region. The drawback of this arrangement is the relatively long channel length of the select transistor and the resulting poor controllability and slow response time of the select transistor.
U.S. Pat. No. 6,137,128 has disclosed a memory cell having a trench capacitor which has a trench which is formed into a semiconductor substrate, in the lower trench region of which a lower capacitor electrode adjoins a wall of the trench and into which trench a storage dielectric and an electrically conductive trench filling comprising polycrystalline silicon as upper capacitor electrode are introduced. A vertical MOSFET is arranged above the trench capacitor as select transistor, both the gate and the source, drain and channel region being formed as regions which encircle a central insulation layer in the shape of a ring. Therefore, a drawback is that the source-drain current of the MOSFET fans out in the shape of a ring, and a further drawback is that it is necessary to form an insulation collar in order to insulate the lower source/drain region of the MOSFET from the lower buried capacitor electrode of the trench capacitor.
The generic document EP 0 905 772 A2 has likewise described a DRAM memory cell and a method for its fabrication in which a vertical MOSFET is formed as select transistor above a trench capacitor, which is filled with polycrystalline silicon as upper capacitor electrode. The MOSFET has a first n-doped source/drain region, a p-doped channel region and a second n-doped source/drain region, which are deposited on the poly-crystalline silicon of the trench filling substantially by epitaxy. This layer sequence is vertically structured in such a manner that it has a square cross section, and a gate electrode layer, which covers the four sides and surrounds the layer sequence, is deposited at the level of the channel region. One drawback of this method is that the MOSFET is grown substantially epitaxially on the polysilicon of the trench filling, with the result that defects and grain boundaries are introduced into the MOSFET. A further drawback is that prior to the fabrication of the MOSFET a vertical etching into a highly doped polysilicon layer which covers the substrate with the trench capacitor is carried out directly above the trench capacitor, and then the gate oxide is applied directly to the etched side walls, and consequently the gate oxide is not of an optimum quality. A further drawback is that the form of the gate electrode of the vertical MOSFET which surrounds the channel region does not allow optimum passage of the gate electrode potential through the channel region. A further drawback is that the memory cell arrangement illustrated and the arrangement of the memory cells in rows along the word line formed by the gate electrodes does not allow a high packing density to be achieved.